module MainCode (

	input CLK_50MHz,			//50MHz clock input
	input CLK_100Hz_test,								//input CLK_100Hz, <--you can use this for your module ModeSim validation
	input CLK_1Hz_test,								//input CLK_1Hz,	 <--you can use this for your module ModeSim validation
	//input load_flag,
	//input [15:0]ResetVal,
	//input [15:0]LoadVal,
	input rst_n,				//An active-low sginal to reset the module
	input StartStop,			//A control signal to start (active) and stop (pause) the module
	input ModeSel,				//A control signal to swich between the two modes (10s stopwatch and 2 mins timer)				
	
	output [6:0] HexMSBH,	//The 7-Seg display Signal for higer-digit in MSB
	output [6:0] HexMSBL,	//The 7-Seg display Signal for lower-digit in MSB
	output [6:0] HexLSBH,	//The 7-Seg display Signal for higer-digit in LSB
	output [6:0] HexLSBL,	//The 7-Seg display Signal for lower-digit in LSB
	output DOT,					//The falshing decimal signal at the lower-digit MSB				
	output [9:0] LED //led control
);

wire [7:0] LSB_binary;
wire [7:0] MSB_binary;
wire clk_100Hz;
wire clk_1Hz;
wire selected_clk;
wire [15:0]ResetVal;
wire [15:0]LoadVal;
wire load_flag;
assign ResetVal = 'd0;
assign LoadVal = 'd0;
assign load_flag = 0;

assign DOT = 1'b0;




ClockDivider CB(
	.CLK_50MHz(CLK_50MHz),
	.rst_n(rst_n),
	.CLK_100Hz(clk_100Hz),
	.CLK_1Hz(clk_1Hz)
);

//assign selected_clk = (ModeSel == 0) ? CLK_100Hz_test : CLK_1Hz_test;
assign selected_clk = (ModeSel == 0) ? clk_100Hz : clk_1Hz;

TimerCoreLogic TC(
	.load_flag(load_flag),
	.ResetVal(ResetVal),
	.LoadVal(LoadVal),
	.ModeSel(ModeSel),
	.clk(selected_clk), 
	.rst_n(rst_n),
	.clk_50Mhz(CLK_50MHz),
	.StartStop(StartStop),
	.LSBbinaryout(LSB_binary),
	.MSBbinaryout(MSB_binary),
	.LED(LED)
);

SevenSegEncoder SE (
	.LSBBinary(LSB_binary),
	.MSBBinary(MSB_binary),
	.ModeSel(ModeSel),
	.HexMSBH(HexMSBH),
	.HexMSBL(HexMSBL),
	.HexLSBH(HexLSBH),
	.HexLSBL(HexLSBL)
);

endmodule